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助研究員  |  鄭湘筠  
 
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Publications
 
Journal Articles
 
1. Wei-Ting Ling, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, Chin-Fu Nien, "DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators," to appear in ACM Transactions on Embedded Computing Systems (TECS).
2. Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang, Chien-Lun Lo, "TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration," IEEE Transactions on Computers (TC), volume 68, number 12, pages 1704 - 1719, December 2019.
3. Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang, "Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling," IEEE Computer Architecture Letters, volume PP, number 99, pages 1-4, April 2017.
4. Hsiang-Yun Cheng, Mary Jane Irwin, Yuan Xie, "Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference," ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 21(1), pages 7:1-7:26, November 2015.
5. Hsiang-Yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahumut Kandemir, Jack Sampson, Yuan Xie, "EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors," ACM Transactions on Architecture and Code Optimization (TACO), volume 12(2), pages 17:1-17:22, July 2015.
 
 
Conference Papers
 
1. Jui-Nan Yen, Yao-Ching Hsieh, Tseng-Yi Chen, Cheng-Yu Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo, "Efficient Bad Block Management with Cluster Similarity," to appear in IEEE International Symposium on High-Performance Computer Architecture (HPCA),.
2. Ting Wu, Chin-Fu Nien, Kuang-Chao Chou, Hsiang-Yun Cheng, "RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment," to appear in IEEE/ACM Design, Automation Test in Europe (DATE),.
3. Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai, "This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator," IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pages 702-707, January 2022.
4. Chen-Yang Tsai, Chin-Fu Nien, Tz-Ching Yu, Hung-Yu Yeh, Hsiang-Yun Cheng, "RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration," ACM/IEEE Design Automation Conference (DAC), pages 589-594, December 2021.
5. Yi-Jou Hsiao, Chin-Fu Nien, Hsiang-Yun Cheng, "ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator," IEEE International Conference on Computer Design (ICCD), pages 260-268, October 2021.
6. Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-Wei Huang, "Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning," IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 276-287, March 2021.
7. Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia- Lin Yang, Tei-Wei Kuo, "Future Computing Platform Design: A Cross-Layer Design Approach," IEEE/ACM Design, Automation Test in Europe (DATE), pages 312-317, February 2021.
8. Chin-Fu Nien, Yi-Jou Hsiao, Hsiang-Yun Cheng, Cheng-Yu Wen, Ya-Cheng Ko, Che-Ching Lin, "GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing," IEEE/ACM Design, Automation Test in Europe (DATE), pages 1478-1483, March 2020.
9. Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael Niemier, Cheng Zhuo, X. Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang, "The Impact of Emerging Technologies on Architectures and System-Level Management," IEEE/ACM International Conference on Computer- Aided Design (ICCAD), pages 1-6, November 2019.
10. Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, "Sparse ReRAM Engine: Joint Exploration of Activation and Weight Sparsity in Compressed Neural Networks," ACM/IEEE International Symposium on Computer Architecture (ISCA), pages 236-249, June 2019.
11. Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, "DL-RSIM: A Simulation Framework to Enable Reliable ReRAM-based Accelerators for Deep Learning," IEEE/ACM International Conference On Computer Aided Design (ICCAD), pages 31:1-31:8, November 2018.
12. Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq-Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung, "Analyzing OpenCL 2.0 Workloads Using a Heterogeneous CPU-GPU Simulator," IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS), pages 127-128, April 2017.
13. Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie, "LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches," ACM/IEEE International Symposium on Computer Architecture (ISCA), pages 103-114, June 2016.
14. Meng-Fan Chang, Ching-Hao Chuang, Yen-Ning Chiang, Shyh-Shyuan Sheu, Chia-Chen Kuo, Hsiang-Yun Cheng, John Sampson, Mary Jane Irwin, "Designs of Emerging Memory Based Non-Volatile TCAM for Internet-of-Things (IoT) and Big-Data Processing: A 5T2R Universal Cell," IEEE International Symposium on Circuits and Systems (ISCAS), pages 1142-1145, May 2016.
15. Hsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin, "Core vs. Uncore: The Heart of Darkness," ACM/IEEE Design Automation Conference (DAC), pages 121:1--121:6, June 2015.
16. Hsiang-Yun Cheng, Matt Poremba, Ivan Stalev, Yuan Xie, Jack Sampson, Mary Jane Irwin, "Energy-Efficient Inclusion Properties for STT-RAM Last-Level Caches," Non-Volatile Memories Workshop (NVMW), March 2015.
17. Hsiang-Yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahumut Kandemir, Jack Sampson, Yuan Xie, "EECache: Exploiting Design Choices in Energy-Efficient Last-Level Caches for Chip Multiprocessors," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pages 303-306, July 2014.
18. Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang, "Memory Latency Reduction via Thread Throttling," ACM/IEEE International Symposium on Microarchitecture (MICRO), pages 53-64, December 2010.
19. Hsiang-Yun Cheng, Jian Li, Chia-Lin Yang, "An Analytical Model to Exploit Memory Task Scheduling," Workshop on Interaction between Compilers and Computer Architecture (INTERACT), pages 7:1-7:8, March 2010.
 
 
Technical Reports
 
1. Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie, "Dswitch: Write-Aware Dynamic Inclusion Property Switching for Emerging Asymmetric Memory Technologies," number CSE16-004, Pennsylvania State University, May 2016.
 
 
 
Others
 
1. Hsiang-Yun Cheng, "Exploiting and Accommodating Asymmetries in Memory to Enable Efficient Multi-core Systems," Pennsylvania State University Ph.D Thesis, August 2016.
2. Hsiang-Yun Cheng, "Cache and Memory Management Policies for Multi-Core Systems,", SIGDA Ph.D. Forum at DAC June 2015.
 
 
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